FIG. 1. is a schematic diagram of a relaxation oscillator of the prior art. The PMOS transistors P1 and P2 and the biasing current source IBIAS are configured as a current mirror. The PMOS transistor P1 and the biasing current source IBIAS are connected serially to form the reference leg of the current mirror. The PMOS transistor P2 is connected as the mirror leg of the current source to provide the mirror current IM1 that mirrors the current from the current source IBIAS. The mirror current IM1 flows from the PMOS transistor P2 to a first common terminal CT of the double pole switch S1. A normally closed terminal NCT is connected to a first plate of a capacitor C2 and a first contact terminal NOT of the normally open switch S3. A second plate of the capacitor C2 and the common terminal CT of the normally open switch S3 are connected to a ground reference source. A normally open terminal NOT is connected to a first plate of a capacitor C1 and a first contact terminal NCT of the normally closed switch S2. A second plate of the capacitor C1 and the common terminal CT of the normally closed switch S2 are connected to a ground reference source.
The normally open terminal NOT of the double pole switch S1 is also connected to the inverting input (−) of the first comparator COMP1 and the normally closed terminal NCT of the double pole switch S1 is connected to the inverting input (−) of the second comparator COMP2. The noninverting inputs of the first comparator COMP1 and the second comparator COMP2 are connected to the reference voltage source VREF. The output of the first comparator COMP1 is connected to the reset input RST of the set/reset latch L1 and the output of the second comparator COMP2 is connected to the set input SET of the set/reset latch L1.
The output CLK of the set/reset latch L1 is output signal of the relaxation oscillator of the prior art. The output CLK of the set/reset latch L1 also acts as a switch control for the double pole switch S1, the normally closed switch S2, and the normally open switch S3. The output CLK of the set/reset latch L1 is connected to the control terminals of the double pole switch S1, the normally closed switch S2, and the normally open switch S3.
In operation, the output CLK of the set/reset latch L1 is initially set to the reset state (0) such that the double pole switch S1 is in its normally closed state, the normally closed switch S2 is in its normally closed state, and the normally open switch S3 is in its normally open state. When the double pole switch S1 is in the normally closed state, the common terminal CT of the double pole switch S1 is connected to the normally closed terminal NCT thus passing the mirror current IM1 to the capacitor C2. The capacitor C2 charges until the voltage developed across the capacitor C2 is greater than the reference voltage VREF. At which time, the comparator COMP2 has a voltage I state (0) that is inverted by the set input SET of the set/reset latch L1 to force the output CLK to the set state (1) to activate the double pole switch S1, the normally closed switch S2, and the normally open switch S3.
The double pole switch S1 is toggled such that the normally open terminal NOT now transfers the mirror current IM1 to the capacitor C1. The normally closed switch S2 is opened to allow the mirror current IM1 to charge the capacitor C1. The normally open switch S3 is closed and the capacitor C2 is discharged to ground. The voltage across the capacitor C1 charges until the voltage across it is greater than the reference voltage VREF. At which time, the comparator COMP1 has a voltage state (0) that is inverted by the reset input RST of the set/reset latch L1 to force the output CLK to the reset state (0) to deactivate the double pole switch S1,
The double pole switch S1 is toggled such that the normally closed terminal NCT now transfers the mirror current IM1 to the capacitor C2 to start the next cycle. The circuit continues to oscillate with each of the capacitors charging and discharging based on the setting and resetting of the set/reset latch L1.
The reference voltage VREF is generated by a voltage source (not shown) that is generally a circuit separate from the relaxation oscillator. In many implementations of the voltage source that generates the reference voltage VREF, the voltage source is a bandgap voltage reference that is a temperature independent voltage reference circuit. The bandgap reference voltage is sensible to use in a very low power device because of its small bias current.
However, a negative factor affecting the operation of the relaxation oscillator as described above is kickback noise from the comparators COMP1 and COMP2 that can shift the reference voltage VREF. The kickback noise is the switching signals during the operation inside a comparator that is fed through capacitances of the input MOS transistors of the comparators COMP1 and COMP2 back to their inputs thus affecting the voltage level of the reference voltage VREF.
A second negative factor affecting the operation of the relaxation oscillator as described above is the power consumption comparators COMP1 and COMP2. A third negative factor affecting the operation of the relaxation oscillator is that the comparators COMP1 and COMP2 have an output signal duty cycle that is not 50% due to mismatches of capacitors C1 and C2 and the voltage offsets of the comparators COMP1 and COMP2. In some applications for the relaxation oscillator, both rising and falling edges are used for timers to halve oscillator frequency and power. Accuracy is improved for such dual edge timers if 50% duty cycle is guaranteed.